The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2002
Filed:
Jun. 12, 2000
Daniel J. Kolor, Wappingers Falls, NY (US);
Scott J. Hadderman, Pleasant Valley, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A current generation, quad RAS, single CAS, stacked component ( ) including four 4 Mb×4 bits 11/11 DRAMs ( ) is arranged to emulate a next generation 16 Mb×4 bits 12/12 DRAM. The (24) bit address signal provided by memory controller ( ) includes a row address of 12 bits and a column address of 12 bits. Each DRAM ( ) within the current generation DRAM component ( ) requires only 11 row address bits and 11 column address bits. The additional 1 row address bit and 1 column address bit are provided to decoder logic ( ). The additional row address bit is decoded by the decoding logic ( ) to direct the RAS signals over two of the four RAS lines ( ), thereby activating the two signaled DRAMs. The additional column address bit is then decoded by decoding logic ( ) to de-activate one of the two signaled DRAMs , leaving only one DRAM activated. CAS line ( ) directs the CAS signal to all of the stacked DRAMs ( ). The combination of both RAS and CAS is provided to only one of the plurality of current generation DRAMs, thereby permitting access to that particular current generation DRAM.