Low-level circuit implementation of signal flow graphs for real-time signal processing of high-speed digital signals

Abstract

Signal processing techniques are applied to data rates at state-of-the-art circuit speeds (presently 1.6 Gbit/sec) by carrying out the signal flow graph of a cannonical FIR filter algorithm using hybrid analog and digital circuit techniques. A plurality of digital to analog converters (DACs) generate analog currents that are the analogue of the tap coefficients of the FIR filter model. The DACs are used as programmable current sources for the tail current sources of respective differential pair stages. Differential delay signals that are the analogue of the FIR delay-line tap signals are connected to the inputs of respective ones of the differential pair stages. The drains of the input devices of the differential pair stages are connected in parallel to common complementary load circuits. The delay signals act to steer the tap coefficient currents to one or the other of the common load circuits. The parallel connection to common load circuits acts to sum the currents sunk (if any) by each of the commonly connected input devices. This current summation is the analogue of the FIR accumulator. Because the tap coefficient currents are readily programmable, the filter may be adaptive. An illustrative embodiment uses the invention in a transceiver for high-speed full-duplex (bi-directional simultaneous) signaling over a single channel interconnect. An adaptation algorithm is used at system initialization to train the tap coefficients according to the particular channel characteristics. The invention enables reliable extraction of receive-signals from the inherent ringing induced by the channel interconnect and at higher data rates than previously possible.