The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2002

Filed:

Oct. 04, 2001
Applicant:
Inventors:

Jeffrey Hwang, Saratoga, CA (US);

Calvin Hsu, San Mateo, CA (US);

Assignee:

Fairchild Semiconductor Corporation, South Portland, ME (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/335 ;
U.S. Cl.
CPC ...
H02M 3/335 ;
Abstract

A controller for a pulse width modulating (PWM) power converter. The controller monitors an output voltage and a current through a magnetic element for modulating a duty cycle of a main power switch. The controller is an eight-pin integrated circuit which controls either a forward converter or a post regulator without internal modifications. The monitored current of the forward converter forms a positive sensing signal. The monitored current of the post regulator forms a negative sensing signal. A current sense circuit of the controller forms an absolute value of either sensing signal. A soft-start circuit of the controller forms a start-up voltage ramp which is proportional to the level of a V supply without requiring an external capacitor. A duty cycle of the main switch is gradually increased by comparing the start-up voltage ramp to the absolute value of the sensing signal. A pulse skipping circuit of the controller disables switching of the main switch under light load conditions. An error signal representative of a difference between the output voltage and a desired output voltage is compared to a pulse skip reference voltage. When the error signal falls below the reference voltage, the main switch is disabled. Because the pulse skip reference voltage is inversely related to the V supply, pulsing of the main switch under light load conditions is spread out in time. A clock signal utilized to control switching of the main switch is generated internally or externally to the integrated circuit.


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