The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2002
Filed:
Jun. 16, 1998
Applicant:
Inventor:
Hiroyuki Yoshine, Kanagawa, JP;
Assignee:
Sony Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 5/00 ;
U.S. Cl.
CPC ...
G09G 5/00 ;
Abstract
In a horizontal driving system of a liquid crystal display, the high frequency of a master clock MCLK and complex wiring to an external substrate for transmitting the master clock MCLK cause disadvantageous unwanted radiation. A sample and hold circuit for sampling and holding a video signal based on the master clock MCLK is provided with a built-in PLL circuit for generating the master clock MCLK in order to eliminate complex wiring for transmitting the master clock MCLK and to reduce unwanted radiation.
Yoshine, Hiroyuki. (2002). Sample hold circuit (U.S. Patent No. 6469699). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6469699
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile