The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 22, 2002

Filed:

Aug. 15, 2001
Applicant:
Inventors:

Norihide Kinugasa, Kyoto, JP;

Kenichi Tatehara, Osaka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 ;
U.S. Cl.
CPC ...
H03M 1/66 ;
Abstract

The digital-analog converter circuit includes: a high-order D-A converter circuit unit ( ) for outputting a first voltage (Va) and a second voltage (Vb) both resulting from D-A conversion of the high-order five bits of a 13-bit input code to first and second output nodes ( ) through two buffers ( ) having the same characteristics, respectively; a low-order D-A converter circuit unit ( ) for receiving the voltages on these two output nodes as reference voltages of an R-2R ladder circuit ( ) and conducting D-A conversion of the low-order eight bits of the input code for output to a third output node ( ); a sample-and-hold unit ( ) for selectively sampling and holding the voltage on the third output node ( ), i.e., the D-A conversion output of the 13-bit input code, according to a value of the input code; and an output unit ( ) for multiplying the sampled and held D-A conversion output voltage by a gain with respect to an arbitrary central voltage. Thus, a D-A converter circuit capable of outputting a desired analog voltage with high accuracy even when a large number of bits are converted is implemented with a small chip area.


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