The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 22, 2002
Filed:
Jul. 01, 1996
Applicant:
Inventors:
E. Ajith Amerasekera, Plano, TX (US);
Charvaka Duvvury, Plano, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/362 ;
U.S. Cl.
CPC ...
H01L 2/362 ;
Abstract
An ESD protection circuit ( ) and method is described herein. A lateral npn transistor ( ) is connected between an I/O pad ( ) and ground (GND). A substrate biasing circuit ( ) increases the voltage across a substrate resistance ( ) during an ESD event by conducting current through the substrate. This, in turn, triggers the lateral npn ( ) which clamps to voltage at the pad ( ) and dissipated the ESD current. The lateral npn ( ) is the primary protection device for dissipating ESD current.