High speed bus interface for non-volatile integrated circuit memory supporting continuous transfer

Abstract

A memory system with non-volatile integrated circuit memory devices including an interface for a high speed bus is described, supporting continuous writes at the bus speed, without the possibility of buffer overrun during most conditions. The system comprises an memory bus, an system buffer, an array of non-volatile storage units, such as flash memory devices, and an interconnect system supporting data transfer among the components. The array includes sets and subsets of non-volatile storage units, referred to herein for convenience as platters having multiple banks, banks having multiple columns, and columns having multiple storage units. The storage units comprises integrated circuit memory having page buffers, with input ports. In one example, the array includes two platters, eight banks per platter, four columns per bank, and eight storage units per column, for a total of 256 storage units. The system buffer includes at least the same number of stores as columns in each bank. The stores comprise FIFOs with from one to sixteen cycles deep. A triple nested loop is used to manage continuos transfer of data from the high speed bus into the much slower non-volatile integrated circuit memory.