Method and apparatus using a distributed system structure to support bus-based cache-coherence protocols for symmetric multiprocessors

Abstract

A method and apparatus for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. Each of the processors may have multiple caches. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device and queues commands received from a master device. The node controller has a deterministic delay between latching a snooped command broadcast by the address switch and presenting the command to the master devices on the node controller's master device buses. The memory subsystems contain a memory controller and a fixed delay pipe from the address port to the memory controller so that the memory subsystem has a deterministic delay between receiving a command from the address switch and presenting the command to the memory controller. The buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a variety of bus protocols.