The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2002

Filed:

Aug. 13, 1999
Applicant:
Inventors:

Mandy Alexander Gray, Southampton, GB;

Michael J. Palmer, North Baddesley, GB;

Ian David Judd, Otterbourne, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/336 ; G06F 1/3362 ;
U.S. Cl.
CPC ...
G06F 1/336 ; G06F 1/3362 ;
Abstract

The present invention provides a method and a system for connecting together, in a VLSI chip, a plurality of macros which require data flow connections between each other. A simple standard interface is realised between all macros. Any number of macros can be connected together, also allowing concurrent transactions between 4 or more macros using a cross-bar switch. Each macro may be a master (capable of requesting connections), a slave (capable of receiving connections from a master) or both. The centralised inter-connect logic includes three major components: the cross-bar switch, which makes the connections between the macros, the address decoder, which determines which slave each master wishes to connect to and an arbiter, which arbitrates between the macros when two or more masters request a connection simultaneously.


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Gray, Mandy. (2002). Vlsi chip macro interface (U.S. Patent No. 6467001). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6467001

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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