Method and circuitry for generating clock

Abstract

Clock generating circuitry includes a frequency dividing circuit for dividing the frequency of an input clock by each of a plurality of predetermined frequency dividing ratios which differ from each other to generate a plurality of frequency-divided clocks such that a frequency-divided clock generated with the smallest frequency dividing ratio, i.e., a frequency-divided clock having the highest frequency, is slightly delayed against all of the other generated frequency-divided clocks. When changing the frequency of an output clock, a multiplexer switches from a previously selected one of the plurality of generated frequency-divided clocks to a desired clock in responsive to a control signal. The desired frequency-divided clock is then furnished as the output clock. Even when the plurality of frequency-divided clocks are not in phase with each other because of unit-to-unit variation when manufacturing the frequency dividing circuit, or due to changes in the operating conditions such as ambient temperature and voltages, the first clock pulse generated when the multiplexer performs the switching operation cannot have a shorter pulse width than pulses of the frequency-divided clock having the highest frequency.