The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2002
Filed:
Nov. 21, 2000
Atsushi Yoshikawa, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
The present invention provides a multistage pipeline latch circuit that tolerates the displacement of a clock edge by exploiting the insertion positions of the latch circuits and the clock input timing to the latch circuits. A latch circuit, operating as a two or more stage pipeline, provides an input flip flop circuit to which an input signal is applied, an output flip flop circuit that supplies an output signal, and a latch circuit provided between the input and output flip flop circuits, a clock signal supply means that supplies a common clock signal to the input and output flip flop circuits and the latch circuits, and a circuit insertion position selection means that determines the insertion position of the input and output flip flop circuits and the latch circuits so that the input of the latch circuit is defined at the center of the through period of the latch circuits are provided.