The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2002
Filed:
Jul. 12, 1999
Frank Peters, Lompoc, CA (US);
Jonathan Geske, Lompoc, CA (US);
Gore Enterprise Holdings, Inc., Newark, DE (US);
Abstract
In a vertical cavity surface emitting laser (VCSEL), the metal contact area, the associated metal bonding pad and the interconnecting metal bridge are deposited on top of a conductive upper mirror stack. To prevent current flow from the pad through the conductive mirror stack which would bypass the active medium, a moat is etched surrounding the pad area. The moat isolates the pad area and the conductive material beneath the pad area. In a method of making a VCSEL, the semiconductor layered portion of an optical semiconductor device is first formed on a suitable substrate. Such semiconductor layers can include various layers of conductive, semiconductive or insulating material as may be required for the type of device being constructed. The metal contact and the metal bonding pad areas together with an interconnecting metal bridge are then deposited on the surface of the semiconductor layers. The structure is then etched down from the top surface to form a moat surrounding the bonding pad area which electrically isolates the semiconductor layered material beneath the bonding pad. An alternative method of making a VCSEL is to form the semiconductor layers and then etch the areas surrounding the bonding pad from the bottom upwardly toward the metal bonding pad. According to this method the etch need only go high enough to prevent the current flow bypassing the active medium of the optical semiconductor device. Once the moat has been formed, the structure is completed by securing it to a suitable substrate.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile