The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2002

Filed:

Nov. 08, 1999
Applicant:
Inventors:

Kazumi Sugai, Tokyo, JP;

Nobukazu Ito, Tokyo, JP;

Hiroaki Tachibana, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/144 ; H01L 2/1302 ; H01L 2/14763 ;
U.S. Cl.
CPC ...
H01L 2/144 ; H01L 2/1302 ; H01L 2/14763 ;
Abstract

A manufacturing method of a semiconductor device which includes wiring dense part and wiring isolated part enables occurrence of 'Erosion' to be prevented, as well as it is capable of being prevented occurrence of 'micro-scratch' on surface of oxide layer. The manufacturing method sets a plurality of trench-parts on insulation layer, before forming metal plating layer consisting of copper so as to embed trench-parts. Manufacturing process implements annealing in such a way that grain-size of the metal plating layer in the wiring dense part becomes smaller than the grain-size in the wiring isolated part. The annealing, for instance, is implemented with substrate temperature of 70 to 200° C. Subsequently, the manufacturing step perfects the semiconductor device while polishing the metal plating layer to cause the surface of the substrate to be flat.


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