The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 15, 2002
Filed:
Aug. 02, 2001
Karl-Ernst Ehwald, Frankfurt, DE;
Bernd Tillack, Frankfurt, DE;
Bernd Heinemann, Frankfurt, DE;
Dieter Knoll, Frankfurt, DE;
Dirk Wolansky, Frankfurt, DE;
Institut fuer Halbleiterphysik Franfurt (Oder) GmbH, Frankfurt, DE;
Abstract
This invention relates to a bi-polar transistor and a procedure for its manufacture. The task of the invention is to propose a bi-polar transistor and a procedure for its manufacture that eliminates the disadvantages of conventional arrangements for a simple polysilicon technology with differential epitaxy for the manufacture of the base, in order to further improve especially the high-speed properties of a bi-polar transistor, to produce highly conductive connections between the metal contacts and the active (inner) transistor region as well as a minimized passive transistor surface, and to simultaneously avoid any additional process complexity and increased contact resistance. This invention resolves the task in that, by creating suitable epitaxy process conditions, the polysilicon layer is deposited on the insulator zone with a greater thickness than the epitaxy layer in the active transistor zone. The greater thickness of the polysilicon layer as compared to the epitaxial layer is achieved by using a very low temperature for the deposition of a part of or the entire buffer layer. The use of a low temperature for the deposition allows a better nucleation of the insulator layer and a reduction of the idle time for the deposition. This allows achieving a greater thickness on the insulator layer as compared with the active transistor zone.