The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 15, 2002

Filed:

Apr. 17, 2001
Applicant:
Inventor:

Jayarama N. Shenoy, Santa Clara, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A MOSFET structure having substantially reduced parasitic junction capacitance, relaxed thermal budget constraints and resiliency to hot carrier damage is disclosed. The MOSFET structure includes a gate stack that is disposed over a gate oxide that is in turn disposed over an active region of a substrate. A pair of shallow trenches are defined on either side of the gate stack, and an intrinsic silicon material is disposed within the pair of shallow trenches up to a top surface of the gate stack. The MOSFET structure further includes source and drain implanted impurities that are defined in an upper portion of the intrinsic silicon material. The upper portion is configured to extend down into the intrinsic silicon material to a target diffusion level that is just below the gate oxide of the gate stack.


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