The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2002
Filed:
Mar. 14, 2001
Applicant:
Inventor:
David A. Morgan, Fort Collins, CO (US);
Assignee:
LSI Logic Corporation, Milpitas, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
In this method for hierarchical extraction of interconnect parasitic data for integrated circuits, a representation of coupled interconnects and polygon data copied from an upper level to a lower level is simplified so that the coupled interconnects and the polygon data are considered to be ground wires. This method also features instance-specific management of hardmac data from copied hardmac views to create SPEF files using both chip level and macro level back-annotation in a hierarchical representation.