Low power pipelined multiply/accumulator with modified booth's recoder

Abstract

A low power high speed multiply/accumulator ( ) utilizes a modified Booth's recoder ( ) to identify situations to power down the partial product array ( ). The modified Booth's recoder ( ) is responsive to a NOP signal ( ) and a add/subtract signal ( ) that result from instruction decode. The partial product array ( ) can be partially or fully shut-down to conserve power in response to the recoder ( ) detecting certain operands and NOP instructions. It also allows implementation a multiply-and-subtract instruction. The output of the partial product array ( ) is registered in a high order product register ( ) and a low order product register ( ). The low order product register ( ) accumulates partial products for multiply-and-accumulate and multiply-and-subtract instructions. The carry bit of the low order product register ( ) is added ( ) to the high order product register ( ) to generate the high order result ( ), while the low order result ( ) are derived from the low order product register ( ).