The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2002

Filed:

Sep. 10, 2001
Applicant:
Inventors:

Young Ju Lee, Goyang, KR;

Jeung Joo Lim, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A FIFO memory device includes a write address generating circuit generating a write address in response to a write clock signal and a read address generating circuit generating a read address in response to a read clock signal. A memory cell array includes a plurality of memory cells arranged between a plurality of write and read word lines and a plurality of write and read bit lines, the memory cell array storing write data in response to the write address and outputting read data in response to the read address. A flag signal generating circuit compares a next write address with a current read address to generate a full flag signal in response to the write clock signal when the next write address and the current read address are equal, and compares a current write address with a next read address to generate an empty flag signal in response to the read clock signal when the current write address and the next read address are equal.


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