The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2002
Filed:
Jul. 03, 2001
Hung-Yi Chang, Hsinchu, TW;
Yi-Hua Chang, Hsinchu Hsien, TW;
Faraday Technology Corp., Hsinchu, TW;
Abstract
An ESD protection circuit layout. The ESD protection circuit layout has a first ESD protection device, a second ESD protection device, a first CDM ESD protection device, a second CDM ESD protection device, a first charge flow prevention device, a PMOS transistor, an input resistor, an NMOS transistor, a second charge flow prevention device and a substrate resistor. Charges within an integrated circuit device are discharged through a discharging loop comprising of the first CDM ESD protection device and the second CDM ESD protection device. Ultimately, the integrated circuit device is protected against CDM ESD and electrical latch-up within the integrated circuit is also minimized.