The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 08, 2002

Filed:

Oct. 02, 2001
Applicant:
Inventors:

Uwe Wahl, Cologne, DE;

Holger Vogt, Muelheim, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ;
U.S. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ;
Abstract

A power MOS element includes a drift region with a doping of a first doping type, a channel region with a doping of a second doping type which is complementary to the first doping type and which borders on the channel region and the drift region, and a source region with a doping of the first doping type, the source region bordering on the channel region. Furthermore, the power MOS element includes a plurality of basically parallel gate trenches which extend to the drift region and which comprise an electrically conductive material which is insulated from the transistor region by an insulator. The individual gate trenches are connected by a connecting gate trench, a gate contact only being connected in an electrically conductive way to the active gate trenches via contact holes in the connecting gate trench. For producing, three photolithographic steps are sufficient, which serve to etch the gate trenches and the connecting gate trench, to produce the contact holes for the source region and said channel region as well as for said connecting gate trench, and to finally structure said gate contacts and said source contact. Thus, a flexible layout concept is possible in which the gate contact can also be placed in the middle of or at another location on the power MOS element without additional expenditure.


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