Sidewall spacer etch process for improved silicide formation

Abstract

Sub-micron dimensioned, ultra-shallow junction MOS and/or CMOS transistor devices having reduced or minimal junction leakage are formed by a salicide process wherein silicon substrate surfaces intended to be subjected to ion implantation for source/drain formation are protected from damage resulting from reactive plasma etching of a blanket insulative layer for sidewall spacer formation by leaving a residual thickness of the insulative layer thereon. The residual layer is retained during ion implantation and removed prior to salicide processing to provide an undamaged surface for optimal contact formation thereon. Embodiments include anisotropically plasma etching a major amount of the thickness of the blanket insulative layer during a preselected interval for sidewall spacer formation and removing the residual thickness thereof after source/drain implantation by etching with dilute aqueous HF.