Method for the integration of resistors and esd self-protected transistors in an integrated device with a memory matrix manufactured by means of a process featuring self-aligned source (sas) formation and junction salicidation

Abstract

A method of forming a doped region in an integrated circuit which includes a matrix of memory cells and lightly-doped drain transistors and which is fabricated by means of a process providing for a Self-Aligned Source masked etch and implant and for a selective salicidation of some doped regions, the doped region suitable for forming an integrated resistor and/or an abrupt-profile source/drain region of a transistor. The doped region is formed by introducing into a semiconductor layer of a first conductivity type a dopant of a second conductivity type and exploiting the SAS masked implant used to form source regions of the matrix of memory cells. At least a portion of a surface of the doped region is prevented from being salicidated by using as a protective mask a portion of a dielectric layer from which insulating sidewall spacers for the LDD transistors are formed.