The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2002
Filed:
May. 02, 2001
Hsing-Yi Chen, Hsin-Chu Hsien, TW;
Jo-Yu Wang, Hsin-Tien, TW;
Jyh-Ming Wang, Tu-Cheng, TW;
Hsin-Kuang Chen, Kaohsiung, TW;
Min-Shun Liao, Hsin-Chu, TW;
Silicon Integrated Systems Corp., Hsin-Chiu, TW;
Abstract
A multi-shifting shift register is adapted for outputting a selected address signal to a memory unit, and includes a control circuit for outputting a number (i) of shift signals and a timing pulse signal. One of the shift signals is at an enabled state and the other ones of the shift signals are at a disabled state during each cycle of the timing pulse signal. A multi-shifting circuit includes a number (N), which is larger than the number (i), of cascaded register units, each of which has a flip-flop that has an input end, and an output end for generating an address signal, and a selector that has the number (i) of select inputs for receiving the number (i) of the shift signals respectively from the control circuit, the number (i) of address signal inputs, and an output. The output end of the flip-flop is connected to a first one of the address signal inputs of the selector. The input end of the flip-flop of each of the register units is connected to the output of the selector of a preceding one of the register units. A j one of the address signal inputs of the selector of each of the registers units is connected to the output end of the flip-flop of a (j−1) preceding one of the register units. The number (j) is a number between 2 and i. The selected address signal is the address signal that is outputted by the flip-flop of one of the register units and that is at the enabled state.