The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2002
Filed:
Dec. 04, 2000
Applicant:
Inventors:
Sundararajan Sriram, Dallas, TX (US);
Zhenguo Gu, Plano, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 2/730 ;
U.S. Cl.
CPC ...
H04L 2/730 ;
Abstract
A circuit is designed with a plurality of logic circuits ( ) for producing an offset state matrix. The circuit includes a first logic circuit ( ) coupled to receive N elements of a respective row of a transition matrix and N elements of column of an input state matrix. The first logic circuit produces a multi-bit logical combination of corresponding bits of the respective row and the column. A second logic circuit ( ) is coupled to receive the multi-bit logical combination and produces a respective element of the offset state matrix.