Semiconductor memory device

Abstract

The invention discloses a semiconductor memory device in which faulty cells causing standby current failure will be replaced with redundancy cells. The semiconductor memory device includes: a plurality of word lines, a plurality of bit lines, a plurality of cells connected between the word lines and bit lines for storing data and a memory cell array of a plurality of cell blocks having a plurality of cell power lines for providing supply voltage to the cells; a plurality of row decoder circuits for decoding external row addresses and generating selection signals for predetermined word lines included in the cell blocks; and a plurality of cell power repairing circuits for selectively blocking between cell power lines providing supply voltage to faulty cells and power source at an occurrence of faulty cells causing standby current failure. At this time, the cell power lines of the cell blocks are arranged in an identical direction to word lines; the row decoder circuits are respectively arranged between two neighboring cell blocks; and the cell power repairing circuits are respectively arranged between the cell blocks of the memory cell array, thereby reducing the size of a chip.