The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2002

Filed:

May. 22, 2001
Applicant:
Inventors:

Itani R. Nadi, Austin, TX (US);

Rex Baird, Austin, TX (US);

Matthew M. Kostelnik, Arvada, CO (US);

Mokry Wesley, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/10 ;
U.S. Cl.
CPC ...
H03M 1/10 ;
Abstract

A system and method is disclosed for calibrating comparators of an ADC while the ADC continues to operate in an uninterrupted fashion. Groups (banks) of interleaved comparators may be calibrated at random or psuedo-random times while the ADC is performing conversions without the addition of extra “proxy” or replacement comparators. More particularly, at periodic intervals the comparators of one bank may be disconnected from the standard ADC circuitry for calibration or auto-zeroing while the comparators in the remaining bank(s) are left in the data conversion path. In order to prevent a significant degradation in the conversion quality, logic downstream of the comparators provides the necessary adjustments to accommodate for the removal of the comparators and outputs a word of the desired bit length. The multi-bank ADC is particularly advantageous for use with optical data storage systems.


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