The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2002
Filed:
Apr. 07, 2000
Adam R. Brown, Bramhall, GB;
Godefridus A. M. Hurkx, Eindhoven, NL;
Wiebe B. De Boer, Eindhoven, NL;
Hendrik G. A. Huizing, Eindhoven, NL;
Eddie Huang, Fallowfield, GB;
Koninklijke Phillips Electronics N.V., Eindhoven, NL;
Abstract
The invention relates to a so-called punch-through diode with a mesa ( ) comprising, in succession, a first ( ), a second ( ) and a third ( ) semiconductor region ( ) of, respectively, a first, a second and the first conductivity type, which punch-through diode is provided with two connection conductors ( ). During operation of said diode, a voltage is applied such that the second semiconductor region ( ) is fully depleted. A drawback of the known punch-through diode resides in that the current flow is too large at lower voltages. In a punch-through diode according to the invention, a part ( A, B) of the second semiconductor region ( ), which, viewed in projection, borders on the edge of the mesa ( ), is provided with a larger flux of doping atoms of the second conductivity type than the remainder ( A) of the second semiconductor region ( ). It has been found that the high current at a low voltage of the known diode is caused by the fact that the second semiconductor region ( ) at the edge of the mesa ( ) is depleted before the remainder of the second semiconductor region ( ). By locally increasing the flux of doping atoms, the depletion at the edge is delayed as compared to the remainder of the second semiconductor region. Preferably, this result is obtained by locally increasing the thickness of the second semiconductor region ( ). In this manner, a substantial current reduction at lower voltages is obtained in the diode in accordance with the invention.