The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 01, 2002

Filed:

Jul. 28, 2000
Applicant:
Inventors:

Stephen K. Park, Austin, TX (US);

George Jon Kluth, Sunnyvale, CA (US);

Bharath Rangarajan, Santa Clara, CA (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1336 ;
U.S. Cl.
CPC ...
H01L 2/1336 ;
Abstract

A process for fabricating a memory cell in a two-bit EEPROM device, the process includes forming an ONO layer overlying a semiconductor substrate, depositing a resist mask overlying the ONO layer, patterning the resist mask, implanting the semiconductor substrate with an n-type dopant, wherein the resist mask is used as an ion implant mask, and performing a resist flow operation on the semiconductor substrate after implanting the semiconductor substrate with an n-type dopant. In one preferred embodiment, the resist flow operation on the semiconductor substrate includes baking the semiconductor substrate in an oven at about 100° C. to about 300° C. for about 5 minutes to about 30 minutes to thin down the resist mask and cause the edges of the resist mask to become rounded.


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