The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 01, 2002
Filed:
Feb. 19, 2002
Axel Brintzinger, Dresden, DE;
Ulrich Frey, Poughkeepsie, NY (US);
Jürgen Lindolf, Friedberg, DE;
Dominique Savignac, Ismaning, DE;
Stefan Dankowski, München, DE;
Matthias Lehr, Dresden, DE;
Jochen Müller, München, DE;
Kamel Ayadi, Puchheim, DE;
Infineon Technologies AG, Munich, DE;
Abstract
The present invention provides a method for fabricating an integrated circuit, comprising the following steps: preparing a circuit substrate ( ); providing a metallization region ( ) comprising a first metal in the circuit substrate ( ); providing a first insulation layer ( ) above the metallization region ( ); forming an opening ( ) in the insulating layer ( ) in order to uncover at least part of the surface of the metallization region ( ); depositing a functional layer ( ′) above the resulting structure; depositing a second insulating layer ( ) above the resulting structure, in such a manner that the opening ( ) is filled; polishing-back of the second insulating layer ( ) and of the functional layer ( ′) in order to uncover the surface of the first insulating layer ( ); forming a contact ( ′) in the second insulating layer ( ) inside the opening ( ) in order to make contact with the functional layer ( ′); and providing an interconnect ( ) for electrical connection of the contact ( ′).