Synchronous memory system with automatic burst mode switching as a function of the selected bus master

Abstract

A computer system with a multi-master system bus includes a memory controller that changes the burst mode of the including memory system automatically as a function of the selected master. The controller includes a programmable look-up table into which is stored a value B corresponding to a fixed memory burst mode; for each master, a multiplier is stored indicating the multiple of the burst mode that would be optimal for that master. The grant signal used to select the current master is also used to select the multiplier M associated with that master. In response to a read request by the current master, a requested address is forwarded to the memory. Then the controller generates and transmits M−1 addresses spaced B addresses apart every Bth bus cycle. This implements a memory system burst of M*B addresses with no latencies between successive B-address memory bursts. The memory system burst can be aborted if an address in the burst is not confirmed by a subsequent address request by the master. This approach improves the performance of a multi-master system by avoiding latencies normally involved in changing burst modes when a switch is made between masters having different burst mode requirements. The approach is preferable to utilizing long bursts that must be aborted frequently. Typically, when a write operation follows a burst, the burst is terminated upon completion—avoiding latencies involved in clearing an aborted burst before a write operation can be executed.