The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2002
Filed:
Aug. 03, 1999
Regis Gaillard, La Gaude, FR;
Nicolas Chauve, Cagnes sur Mer, FR;
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A digital system has a host processor with a bus controller and peripherals ( )- ( ) interconnected by an interconnect bus peripherals are share a common strobe line (nSTROBE [0]) on an embodiment of the interconnect bus in a first subdomain. Additional sub-domains, such as sub-domain , can be likewise connected to interconnect bus . Additional strobe lines nSTROBE(n) are used to select a particular sub-domain in response to an address presented to bus controller by CPU . A FIFO is provided on a peripheral device to reduce data transfer access time. When the FIFO is almost empty, a FIFO management state machine requests a DMA transfer by asserting the nDMA_REQ signal on the interconnect bus, thus transitioning from idle state to transfer state along arc . The DMA controller transfers several data words until the FIFO becomes full, as indicated by word_cpt=FIFO_size. Then the FIFO state machine controller transitions to end transfer state and asserts the END_DMA signal to stop the DMA transfer and then transitions to IDLE state