Dsp intercommunication network

Abstract

A multi-processor system includes a global bus ( ) with a global address space and a plurality of processor nodes ( ). Each of the processor nodes ( ) has a CPU ( ) interfaced with a local bus having a local address space. A dual port SRAM (DPSRAM) ( ) is provided for interfacing between the global bus ( ) and the local bus ( ). Each DPSRAM ( ) for each processor core ( ) has a defined address space within the global bus address space. Whenever any of the global resource writes to the particular processor node ( ), it is only necessary to address the designated DPSRAM ( ) and transfer data thereto. The act of transferring the data thereto will generate an interrupt to the associated CPU ( ) which will then cause it to read the received data on the local bus by addressing its associated DPSRAM ( ). This results in only a single access cycle for data transfer. Each of the CPU's ( ) can communicate directly with another of the CPU's ( ) through an interprocessor communication network. This network includes a Bi-FIFO ( ). The CPU ( ) is operable to interface with a predefined type of memory having a defined memory access protocol different from that of the Bi-FIFO ( ). Therefore, a translator circuit is required to convert memory access commands and data flow to a compatible format with that of Bi-FIFO ( ). This includes a programmable bi-directional pipeline circuit ( ) and also a predecode circuit ( ) to allow selection of one of a plurality of Bi-FIFOs to allow the CPU ( ) to communicate with different Bi-FIFOs within the same memory space.