The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2002
Filed:
Nov. 17, 2000
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
In a pipelined analog-to-digital converter (ADC) having an analog input signal and a digital output signal, and having a plurality of pipelined stages, each such stage having an analog input, an analog output comprising a residue voltage, and a digital output, the stage including a digital-to-analog converter substage having a plurality of capacitors and which are used in a sample-and-hold function and shuffled according to a predetermined procedure, a method for reducing noise generated from the shuffling when the capacitors are mismatched. The method includes the following steps. First, an estimation model is provided of the noise generated from the shuffling. The estimation model includes factors corresponding to mismatches of the capacitors. Mismatches among capacitors in the stage are estimated, based on the monitoring of an output parameter of the stage. A cancellation factor is generated by applying the mismatch estimations to the estimation model. Finally, the cancellation factor is subtracted from an ADC output to substantially reduce and/or effectively cancel the mismatch noise.