The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 24, 2002

Filed:

Aug. 08, 2000
Applicant:
Inventors:

Dale A. Oakeson, Midvale, UT (US);

Don R. Sauer, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 5/00 ;
U.S. Cl.
CPC ...
H03K 5/00 ;
Abstract

A translation circuit for transferring a differential voltage to a ground referenced voltage includes a differential input circuit, a sample/hold (S/H) circuit, and a compensation circuit. The S/H circuit includes a S/H capacitor, a series capacitor and a switch. The S/H and series capacitors are connected in series between an output line and a source of ground potential (GROUND). The switch shorts the bottom electrode of the S/H capacitor to GROUND when executing a translation operation. The differential input circuit receives the differential voltage and selectively provides the differential voltage across the S/H capacitor so that the top and bottom electrodes of the S/H capacitor have voltages V+ and V−, respectively. Parasitic capacitance tends to add charge to the S/H capacitor during the translation operation. The compensation circuit compensates for parasitic capacitance by removing, ideally, the same amount of charge from the S/H capacitor by the end of the translation operation.


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