The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 24, 2002
Filed:
Dec. 08, 1998
Paul L. Perez, El Granada, CA (US);
Hewlett-Packard Company, Palo Alto, CA (US);
Abstract
A noise suppression circuit is presented which improves signal quality on signal control lines of dynamic logic circuits. The noise suppression circuit provides dynamic line termination and immunity to cross-coupling of signals from other control lines. The line termination portion of the circuit suppresses high-transitioning pulses on low-drive control lines by referencing the low control line level to the local ground and low-transitioning pulses on high-drive control lines by referencing the control line level to a local power supply to immunize pass-gate logic. The input of a CMOS inverter is coupled to the control line. The drain of a FET is coupled to the output control line, and its gate is coupled to the output of the CMOS inverter. Suppression of high-transitioning and low-transitioning pulses is achieved by coupling the source of the FET to the local ground or local power supply respectively. Cross-coupling of signals between the control line and another control line is prevented by cross-coupling a pair of FETs between the two control lines, with the drain of the respective FET coupled to its respective control line and the gate of the respective FET coupled to the other control line.