Semiconductor device having electrostatic discharge protection circuit

Abstract

A semiconductor device, including an electrostatic discharge protection circuit capable of preventing current from being concentrated in a hot spot through a silicide layer, includes an N-type MOS transistor having a first diffusion region on a semiconductor substrate. This N-type MOS transistor is isolated from another MOS transistor by a first element isolation region. A second diffusion region is formed between the first diffusion region and first element isolation region. The first and second diffusion regions are separated by a second element isolation region. A silicide is formed on the surface of the semiconductor substrate excluding the first and second element isolation regions. A pad is connected to the second N-type diffusion region through a contact. An electrostatic charge injection through the pad and contact is discharged mainly through a first discharge path guided to a channel (P-type well) of the N-type MOS transistor through the second diffusion region (N-type), N-type well under the second element isolation region, and second diffusion region (N-type). A discharge path passing through the silicide layer rarely functions as a discharge path, since the contact resistance value between the silicide layer and first diffusion region is greater than the resistance value of the first diffusion region.