The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 17, 2002
Filed:
Aug. 16, 2000
Applicant:
Inventors:
Harry N. Gardner, Colorado Springs, CO (US);
Debra S. Harris, Colorado Springs, CO (US);
Michael D. Lahey, Colorado Springs, CO (US);
Stacia L. Patton, Colorado Springs, CO (US);
Peter M. Pohlenz, Colorado Springs, CO (US);
Assignee:
Aeroflex UTMC Microelectronic Systems Inc., Colorado Springs, CO (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/750 ;
U.S. Cl.
CPC ...
G06F 1/750 ;
Abstract
Functional and geometrical sub-components of logic circuits are defined and used in the design of integrated circuits to facilitate the transformation of an integrated circuit design for fabrication at foundries with different design rules.
Gardner, Harry. (2002). Method for fabricating integrated circuits (U.S. Patent No. 6453447). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6453447
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile