The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 17, 2002

Filed:

Aug. 02, 2001
Applicant:
Inventors:

Paul Bacchi, Novato, CA (US);

Paul S. Filipski, Greenbrae, CA (US);

Assignee:

Newport Corporation, Irvine, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/900 ;
U.S. Cl.
CPC ...
G06F 1/900 ;
Abstract

Robot arm ( ) end effectors ( ) of this invention rapidly and cleanly transfer semiconductor wafers ( ) between a wafer cassette ( ) and a processing station. The end effectors include proximal and distal rest pads ( ) having pad and backstop portions ( ) that support and grip the wafer either by wafer peripheral edge contact or within an annular exclusion zone ( ) that extends inward from a peripheral edge of the wafer. An active contact point ( ) is movable by a vacuum actuated piston ( ) between a retracted wafer-loading position and an extended position that urges the wafer against the distal rest pads to grip the wafer at its edge or within the exclusion zone. The end effector further includes fiber optic light transmission sensors ( ) for determining various wafer surface, edge, thickness, tilt, and location parameters. The sensors provide robot arm extension and elevation positioning data supporting methods of rapidly and accurately placing and retrieving a wafer from among a stack of closely spaced wafers stored in the wafer cassette. The methods effectively prevent accidental contact between the end effector and the wafers while effecting clean, secure gripping of the wafer at its edge or within its exclusion zone.


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