Parasitic insensitive capacitor in d/a converter

Abstract

A parasitic insensitive capacitor in a D/A converter. A semiconductor substrate is provided having a first face upon which the semiconductor integrated circuit is formed with a first conductive layer disposed over a portion of the first face of the semiconductor substrate and separated therefrom by a first insulating layer to form the lower plate of the capacitor. A second conductive layer is disposed over a portion and less than all of the first conductive layer and separated therefrom by a second insulating layer to form the upper plate of the capacitor. A third conductive layer disposed above the first and second conductive layers and separated from the first conductive layer by a third insulating layer, the third conductive layer having an opening therein of substantially the same shape as the second conductive layer and wherein the peripheral edges of the opening are substantially aligned with the peripheral edges of the second conductive layer. A conductive interconnect is disposed above the third conductive layer and separated therefrom by a fourth insulating layer and connected on at least a portion thereof to the second conductive layer, the interconnect extending over the third conductive layer such that the third conductive layer separates the interconnect from the first conductive layer.