Circuit for switching between multiple clocks

Abstract

A circuit to synchronously select one of the multiple clocks is presented. In one embodiment the selection circuit consists of four main blocks. These are the stable selects block, the decoder block, the synchronous selects block, and the output block. The stable selects block takes select signals as inputs and outputs a signal indicating whether the selects are stable or not, in addition to producing select signals that are synchronous to the current selected clock. The decoder block, decodes the select signals if they are stable, otherwise it re-circulates the previous values of the decoded clock select signals. The stable decoded select signals are then passed on to the synchronous selects block. This block outputs select signals in synchrony with their respective clocks. The synchronous select signals along with the stable decoded signals are used in the output block along with the clocks themselves to generate the final output clock. The transition from the first clock to the second clock is achieved with out any clips or glitches on the output clock. In order to eliminate the possibility of a glitch the first clock is disengaged from the output clock during the first clock's low state. This low state is maintained on the output clock until it is deemed safe to engage the second clock to the output clock during the second clock's low state.