Column grid array for flip-chip devices

Abstract

A method for providing C4-type bumps which are higher than conventional C4 bumps. A dielectric substrate is copper cladded on both sides. At each prospective bump location, a via is laser ablated through the cladded substrate. A copper core is deposited within the vias to thereby connect the two claddings. A photoresist is applied to both claddings, a photomask having a predetermined exposure pattern is placed over the claddings, the photoresist is exposed to ultraviolet (UV) light to thereby polymerize in the exposed areas thereof, and the resulting photoresist image is developed by use of a developer solution to wash away of the unpolymerized areas of the photoresist. Now, the photoresist image provides a retainer wall spaced from, and circumferentially around, the vias. Next, a lead-tin solder alloy is electroplated, such as by a lead-tin fluoroborate bath, at the vias into the volumes defined by the retainer wall at each end of the vias. Now, the photoresist is stripped, such as by an alkali stripper, from the cladding, leaving behind a pair of solder deposits at each via. Next, the copper cladding is etched away using an ammonia based etchant, wherein the solder deposits are left intact. Finally, the solder deposits are subjected to reflow, whereupon the solder deposits form a pair of generally convexly shaped bumps connected to the copper core. In the preferred environment of practice, the bumps form a column grid array pattern arranged on an electronic device.