Method and apparatus for providing chained breakpoints in a microprocessor

Abstract

A processor core is provided that is a programmable digital signal processor (DSP). The microprocessor is operable to execute a sequence of instructions obtained from an instruction bus and has program counter circuitry for providing a first instruction address to the instruction bus. An instruction buffer is operable to hold at least a first instruction of the sequence of instructions obtained from the instruction bus. Breakpoint event generation circuitry is connected to the instruction bus and is operable to detect a designated mark instruction and a designated chain instruction in the sequence of instructions. Tag circuitry is associated with the instruction buffer and is operable to hold a mark tag and a chain tag, and is further operable to be set in response to the breakpoint event circuitry. An instruction execution pipeline is connected to receive the sequence of instructions from the instruction buffer register along with respective mark tags and chain tags from the tag circuitry. The instruction execution pipeline has a point of no return instruction pipeline stage. Breakpoint state machine circuitry is connected to the point of no return instruction pipeline stage and is operable to monitor mark tags and chain tags received by the point of no return instruction pipeline stage. The breakpoint state machine is further operable to indicate a chained breakpoint event when a chain tag is received after a mark tag form the point of no return instruction pipeline stage.