The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 10, 2002

Filed:

May. 12, 1999
Applicant:
Inventor:

Edward Clayton Morgan, Macungie, PA (US);

Assignee:

Agere Systems Guardian Corp., Orlando, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 ; G06F 7/50 ;
U.S. Cl.
CPC ...
G06F 7/38 ; G06F 7/50 ;
Abstract

An integrated circuit includes an adder having a first adder circuit for receiving a portion of the operands to be summed, along with corresponding carry-in inputs. The first adder circuit provides a sum output and carry-out outputs. A second adder circuit receives another portion of the operands to be summed, along with corresponding carry-in inputs. Multiplexers between the first and second adder circuits determine whether the carry-in inputs to the second adder circuit are the same the carry-in inputs to the first adder circuit or whether the carry-in inputs to the second adder circuit are independent.


Find Patent Forward Citations

Morgan, Edward. (2002). Three input split-adder (U.S. Patent No. 6449629). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6449629

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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