Output synchronization-free, high-fanin dynamic nor gate

Abstract

An article of manufacture describes and simulates a logic device that detects the all-zero scenario for an n-bit word. The n-bit word has a selected bit that is defined using a high-inactive convention, and (n−1) non-selected bits that are defined using a high-active convention. The article of manufacture is embodied as a computer useable medium configured to store computer program codes that describe and simulate the logic device. The logic device described by the computer program codes includes an output FET, a pre-charging circuit, a first evaluation circuit, and (n−1) second evaluation circuits. The pre-charging circuit charges the output FET gate, drain, and source to a pre-charge voltage during a low clock cycle. During a high clock cycle, the first evaluation circuit evaluates the selected bit and discharges the pre-charge voltage on the output FET source if the selected bit is a voltage high. The (n−1) second evaluation circuits evaluate the non-selected bits and maintain the pre-charge voltage on the output FET gate if each of the non-selected bits is a voltage low. The output FET conducts if the pre-charge voltage is maintained on the output FET gate and if the output FET source is discharged to ground. The drain of the output FET discharges to a low voltage if the output FET conducts, which indicates the all-zero scenario for the n-bit word.