The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2002
Filed:
Feb. 05, 2001
Balaraman Mani, Cupertino, CA (US);
Bill Chen, Saratoga, CA (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
For depositing semiconductor films on a plurality of sets of semiconductor wafers, a first set of semiconductor wafers carried by a wafer boat are placed within a reaction chamber. An in-situ doped amorphous semiconductor film is deposited on the first set of semiconductor wafers while the first set of semiconductor wafers carried by the wafer boat are within the reaction chamber. The first set of semiconductor wafers carried by the wafer boat are removed from the reaction chamber, and the first set of semiconductor wafers are removed from the wafer boat. The wafer boat that is empty of any semiconductor wafers is placed back within the reaction chamber. A first undoped semiconductor film having a thickness in a range of from about 8,000 Å (angstroms) to about 12,000 Å (angstroms) is deposited on the wafer boat and on components of the reaction chamber. The wafer boat is then removed from the reaction chamber, and a second set of semiconductor wafers are loaded within the wafer boat. The wafer boat having the second set of semiconductor wafers loaded therein is placed within the reaction chamber. A second undoped semiconductor film is deposited on the second set of semiconductor wafers while the second set of semiconductor wafers carried by the wafer boat are within the reaction chamber. In this manner, the in-situ phosphorous doped amorphous silicon film is deposited on the first set of semiconductor wafers and the undoped polysilicon film is deposited on the second set of semiconductor wafers within the same reaction chamber to minimize cost and labor during integrated circuit manufacture.