The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 10, 2002
Filed:
Jun. 22, 2000
Emmanuel de Muizon, Fremont, CA (US);
Jeffrey Lutze, San Jose, CA (US);
Koninklijke Philips Electronics N.V., Eindhoven, NL;
Abstract
An integrated circuit manufacturing process selectively blocks silicide formation during the fabrication of I/O devices to enhance their ESD performance while not impacting the performance of core devices. In an example embodiment, a spacer dielectric covers the MOS structure so that the gate may be protected from process degradation. The spacer dielectric is masked to define silicidation blocking regions and silicidation accepting regions. Spacer dielectric is removed in regions where silicidation is to be accepted. Silicidation blocking regions protect transistor devices from subsequent ion implantation. Consequently, the ion implantation profiles for core transistors and I/O transistors are maintained for enhanced performance and reliability for each transistor type.