The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2002
Filed:
Jan. 05, 2000
Zhaoyun Xing, San Jose, CA (US);
Russell Kao, Portola Valley, CA (US);
Sun Microsystems, Inc., Santa Clara, CA (US);
Abstract
A method and apparatus for performing power routing in ASIC design. Power routing is performed after cell placement, allowing more knowledgeable placement of power structures in the physical layout. By performing cell placement prior to power routing, standard cells are allowed to be placed in more optimal configurations. In one embodiment, power rings and power straps are placed over the top of the standard cells based on power analysis of the standard cell layout. Those regions of the layout where design violations are triggered are corrected by an incremental placement correction of affected cells. In another embodiment, cells are placed in the physical layout in a bottom-up hierarchical manner. When a given cell becomes large enough to require power routing, a power feed cell of sufficient dimension to support the necessary power strap is inserted into the layout during the placement process. In the subsequent power routing phase, power straps are placed over the power feed cells.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile