The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2002
Filed:
Apr. 16, 2001
Axel Thomsen, Austin, TX (US);
Qicheng Yu, Nashua, NH (US);
Cirrus Logic, Inc., Austin, TX (US);
Abstract
The present invention provides an alternative to Prior Art isolation techniques by providing a capacitively coupled reference voltage and a capacitively coupled gain calibration. The isolation technique of the present invention is based upon the idea of a near unity gain capacitive divider. If the load or parasitic capacitance is Cload and the isolation capacitance is Ciso, then the gain between input and output can be calculated as Vout/Vin=(Ciso)/(Ciso+Cload), which will be nearly unity (i.e., 1) when Ciso>>Cload. In addition, if Ciso>>Cload, the gain will also be largely insensitive to variations in Ciso and Cload. For example, if Cin is 100 ppm of Ciso, then a 10% variation in Ciso or Cload results in only a 10 ppm variation in the voltage gain.