The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 03, 2002
Filed:
Feb. 26, 1998
Applicant:
Inventors:
Yohei Ishikawa, Kyoto, JP;
Koichi Sakamoto, Nagaokakyo, JP;
Sadao Yamashita, Kyoto, JP;
Kenichi Iio, Nagaokakyo, JP;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03B 7/14 ;
U.S. Cl.
CPC ...
H03B 7/14 ;
Abstract
A planar dielectric integrated circuit is provided such that energy conversion loss between a planar dielectric line and electronic components is small and that impedance matching between them can be easily obtained. A planar dielectric line is provided by causing two slots to oppose each other with a dielectric plate interposed in between, a slot line and line-conversion conductor patterns are provided in the end portions of the planar dielectric line, and an FET is disposed in such a manner as to be extended over the slot line.