Apparatus and method for accelerating initial lock time of delayed locked loop

Abstract

An apparatus and method for accelerating an initial lock time of the DLL in a high rate double data rate (DDR) synchronous random access memory (SDRAM) is disclosed. The apparatus for accelerating an initial lock time of the DLL comprises a first clock generator for generating a reference clock signal based on the external synchronization clock signal; a phase comparator for applying a unit delay time and a multiple unit delay time to the internal clock signal and for comparing phases of the internal clock signal, a unit delayed internal clock signal and a multiple unit delayed internal clock signal with a phase of the reference clock signal; a shift controller for selecting an amount of delay time based on a comparison result; a delay unit for delaying the internal clock signal by the amount of delay time based on a selected amount of delay time; and a delay clock modeling unit for generating a modeled delay clock signal corresponding to a delayed internal clock signal and for providing the modeled delay clock signal with the phase comparator for applying a unit delay and a multiple unit delay time.